The present invention generally relates to analog-to-digital converters (ADCs), and more particularly to a system, method, and apparatus for providing accurate ADC stage functionality while avoiding capacitor mismatch and non-linearity problems.
The ubiquitous switched capacitor charge transfer circuit has long been used in a wide range of signal processing applications. Switched capacitor circuits are a class of discrete-time systems that are often used in connection with filters, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other analog/mixed signal applications. Conventional switched capacitor circuits are based on creating coefficients of a transfer function by transferring charge from one input capacitor C1 to a second capacitor C2 in the feedback loop of an amplifier via the virtual node of that amplifier so as to create a transfer of C1/C2. For example, a gain of two can be created by making C1=2*C2.
However, finite amplifier DC gain and bandwidth cause incomplete charge redistribution, resulting in incomplete charge transfer from C1 to C2. This, together with inaccuracies in the matching of the capacitors C1 and C2, results in the creation of an inaccurate transfer function. Many applications, such as ADCs, require very high accuracies in the transfer function, such as accuracies exceeding 0.1%. This kind of accuracy is virtually impossible using conventional circuits in modern day CMOS processes. Often, the values of the capacitors are trimmed at manufacture, or some active calibration routines are executed, switching in and out small value capacitors in order to create an accurate transfer. Such schemes are expensive for high volume manufacture. To reduce capacitor mismatch problems, special capacitors such as double poly or Metal-Insulator-Metal (MiM) capacitors may be used, but the capacitor mismatch problem is not eliminated. Further, such circuits that employ voltage-to-charge and charge-to-voltage translations via the virtual earth node have limited immunity to extraneous noise sources, as the virtual earth node is a well known pick-up point for unwanted noise.
Prior art switched capacitor circuits such as those described above are often used in the design of ADCs, such as pipelined and algorithmic ADCs. The transfer characteristic of such ADCs is affected by non-linearities in the analog hardware. While offsets in the amplifier and comparators may be corrected through the use of digital error correction (DEC) logic, other sources of error remain. These include the inaccuracies in the creation of a multiply-by-two (MX2) gain function (including subtraction of sub-DAC levels), and variations in the reference levels. Variations in the reference levels is only an issue in pipelined ADCs, in which separate hardware in each stage samples +Vref and xe2x88x92Vref. Static errors in the reference levels are not an issue for algorithmic ADCs, since each rotation of the ADC samples the same references in the same way with the same hardware. The absolute accuracy of the reference levels is not important in a differential implementation, as long as they are stable and do not vary from conversion to conversion. Thus, the remaining sources of error that limit the accuracy of the complete ADC are the accuracy of the MX2 function, and the accuracy of the sub-DAC through the accuracy with which the DAC levels can be generated. In actual state of the art implementations, these errors are predominantly caused by the capacitor mismatch problems described above.
The present invention addresses these and other shortcomings of the prior art, and provides a solution to the problems exhibited by prior art switched capacitor ADC circuits.
In various embodiments, the present invention provides a method, apparatus, and system for providing accurate level shifting, residue multiplication, and sample-and-hold functions for analog-to-digital conversions, without requiring charge transfer between capacitors in a switched capacitor arrangement, thereby eliminating capacitor mismatch as a source of ADC errors.
In accordance with one embodiment of the invention, an ADC stage is provided for use in analog-to-digital conversions. The ADC stage includes an amplifier having first and second input terminals, and an output terminal to provide an analog ADC residue signal. First and second capacitances sample an input voltage signal and a complemented input voltage signal respectively, in response to a first clock phase. A first switch circuit is coupled to the first capacitance to provide the sampled input voltage signal to the first input terminal of the amplifier, and to couple the output terminal of the amplifier to the first capacitance via a feedback loop, in response to a second clock phase. A second switch circuit is coupled to the second capacitance to provide an inverted version of the sampled complemented input voltage signal to the second input terminal of the amplifier in response to the second clock phase. A level shifting circuit is coupled to receive the input voltage signal, and in response, to select one of a plurality of reference voltages. The amplifier adds the input signal to the inverted version of the complemented input signal as shifted by the level shifting circuit, to create the analog ADC residue signal for use in a subsequent ADC stage. Differential and/or double-sampling versions are also provided in accordance with the present invention. Further, the present invention may be used in a number of ADC configurations, including algorithmic and pipelined ADC configurations.
In accordance with another embodiment of the invention, a method is provided for converting an analog input signal to a digital signal using an amplifier. The method includes sampling the analog input signal onto a first capacitor, and the complement of the analog input signal onto a second capacitor. The sampled analog input signal is provided to a first input terminal of the amplifier by controllably connecting the first capacitor between the amplifier output and the first input terminal in a unity gain feedback configuration. An inverted version of the sampled complemented analog input signal, level shifted by one of a plurality of selectable reference voltages, is provided at a second input terminal of the amplifier by controllably coupling the second capacitor between a selected reference voltage and the second input terminal of the amplifier. The sampled analog input signal is added to the inverted version of the sampled complemented analog input signal, and the selected reference voltage is subtracted therefrom to provide a residue signal available for use in subsequent conversion stages.
It will be appreciated that various other embodiments are set forth in the Detailed Description and Claims which follow.